As known, a classical Doherty amplifier has two amplifying devices arranged in parallel and of the same power capability. The first one of the devices (main stage) operates in a class-AB amplifier mode and the second one (peak stage) operates in a class-C amplifier mode. These devices are separated at their inputs and at their outputs by 90° phase-shifting networks. The output phase-shifting network has a specific characteristic impedance Z0 which must be equal to the optimal load impedance RLm of the main stage. The input signal is split so as to drive the two amplifiers, and a summing network, known as an “impedance inverter” or a “Doherty combiner”, is operative to: a) combine the two output signals, b) to correct for phase differences between the two output signals, and c) to provide an inverted impedance at the output of the Doherty amplifier with respect to the impedance as seen from the output of the main stage. While the Doherty input power level stays below 0.25 of the maximum (or: 6 dB below maximum) the peak stage remains inactive. Due to the impedance inversion, the main stage operates at load, which is two times higher than the optimal load and equal to RLm=2 Z0. This allows higher power efficiency of the main stage, and also of the Doherty amplifier. The double load at the output of the main stage is possible at proper arrangement of the output load RLD of the Doherty amplifier which, for the classical case, is RLD=½Z0=½RLm and which is transformed by the output phase-shifting network to 2Z0=2RLm=4RLD. When the input signal to the Doherty amplifier achieves a certain power level, which is 6 dB below the peak power level for a classical Doherty amplifier, the output voltage of the main stage reaches the maximum RF voltage amplitude resulting in maximum power efficiency and then the peak stage is activated and takes over the amplification. Above this threshold power level, the load impedance as seen by the main stage starts to drop gradually with growing power level until it reaches its optimal value Z0, which occurs at the peak power level of the Doherty amplifier.
Doherty amplifiers are discussed in, e.g., US patent application publication 20050231286, and U.S. Pat. No. 6,356,149, both incorporated herein by reference.
A Doherty amplifier is a very attractive candidate for integration in a semiconductor device, due to its simplicity and due to the fact that its operation is involving only an analog-signal processing technique. But this comes at a cost: the development of a Doherty amplifier requires very precise design and presents a real challenge even to highly experienced designers of RF (radio frequency) circuitry. The electrical parameters of the components involved in the Doherty amplifier, e.g., ceramic capacitors and their positions on the printed circuit board (PCB), must be precisely defined at tolerances, which are much smaller than those required for traditional power amplifiers. Also, due to mechanical tolerances, the ground contacts of the main stage and of the peak stage packages, and their positions between the input micro-strip lines and output micro-strip lines of the PCB, are not reproducible precisely enough and add to the phase shift inconsistency between the two amplification branches. As a result the accuracy of the values of the Doherty amplifier parameters is adversely affected and this causes a low yield at the production line. This problem can be handled in several ways. The first traditional one is the tedious tuning of the Doherty amplifiers at the production line, which takes time and highly experienced electrical engineers and personnel, and is therefore costly. The second solution is precise designing involving good electrical modeling and implementation with components having low tolerance, which also increases production cost. Accordingly, if integrated, the problems related to the electrical and mechanical tolerances as mentioned above will be reduced, and the advantages of a Doherty amplifier reside in a more consistent performance and a lower price in mass production. Then, the quality of an integrated Doherty amplifier mainly depends on a proper design minimizing the parameter spread of the components used and on the parasitic electromagnetic coupling between its components.
The very general requirements for guaranteeing a proper Doherty performance is a precise input power control that involves the control of the amplitude and phase of the input signals as supplied to the main stage and the peak stage. This turns out to be complicated as a result of the non-linearity of the peak stage, operating as a C-class amplifier, that may be characterized as the power dependence of the input impedance and the output impedance. The dependence of the input impedance on the power requires an adequate design of the input network, or a good isolation between the input port of the main stage and the input port of the peak stage. A hybrid coupler is generally used for this reason. Such a hybrid coupler, however, made by means of distributed transmission lines or by means of lumped capacitor and inductor elements, is difficult to implement in an MMIC (Monolithic Microwave Integrated Circuit) owing to the lack of space required and typically also to the properties of the semiconductor substrate causing high power-losses as in, e.g., Si LDMOS (Laterally Diffused Metal-Oxide Semiconductor) technology.
FIG. 1 is a circuit diagram of a known Doherty cell 100 manufactured in an LDMOS process. Such a cell can be used as a building block to create a high-power Doherty amplifier by means of an array of such cells arranged in parallel. Cell 100 comprises a main amplifier 102 and a peak amplifier 104 arranged in parallel between an input 106 and an output 108. Input 106 is coupled to the input of main amplifier 102 via an input network comprised of a capacitance 110, an inductance 112 and a capacitance 114. Input 106 is coupled to the input of peak amplifier 104 via an input network comprised of an inductance 116, an inductance 118 and a capacitance 120. The output of main amplifier 102 is coupled to output 108 via an output network comprised of a capacitance 122, and inductance 124 and a capacitance 126. Capacitances 122 and 126 are formed by the parasitic drain-source capacitance Cds of amplifier 102 and of amplifier 104, respectively.
Integrated Doherty amplifiers made with current semiconductor technologies are well suited for use in mobile communication devices in the frequency ranges of PCS (Personal Communications Service), operating in the 1900 MHz range and W-CDMA (Wideband Code Division Multiple Access) located in the 1.8 GHz-2.2 GHz range. This can be seen by considering the low-pass C-L-C output network of capacitances 122 and 126 and inductance 124. This output network is used as output combiner of an integrated symmetrical Doherty amplifier. A well-known basic requirement for a Doherty output network is that it provides the functionality of a quarter-wavelength transmission line of a specific characteristic impedance Z0. The value of Z0 is chosen to be the optimum load resistance R0 of the main amplifier stage of the Doherty amplifier. The lumped C-L-C network is equivalent to an impedance inverter. This requires that the capacitance value Cds and the impedance value L be as given in expression (202) of FIG. 2, wherein ω is the angular frequency. For operating in the GHz ranges, a Doherty amplifier is made in a suitable semiconductors technology, e.g., LDMOS. For example, in LDMOS, the supply voltage Vds is around 28 V-32 V; for the selected size of the main stage device the value of the parasitic drain-source capacitance Cds equals 1.86 pF with a maximum drain current Id of 1.2 A; and the knee voltage Vk is 4V. The optimum load resistance R0 is then 40 Ohm according to expression (204). The operating frequency fo is given by expression (206) and lies around 2 GHz. The inductance value L needed is given by expression (208) and equals 2.95 nH for 2.14 GHz, and slightly more at 1.8 GHz. In an example embodiment, inductances 112 and 118 of the input network are integrated in the silicon substrate, and inductances 116 and 124 are formed with bonding wires.
Accordingly, for applications in the 2 GHz range, such as PCS and W-CDMA, this implementation of a Doherty amplifier can be used in Si-LDMOS. However, for other frequency ranges, such as 1 GHz and WiMax (Worldwide Interoperability for Microwave Access) for the bands of 2.5 GHz-2.7 GHz and 3.4 GHz-3.8 GHz, this Doherty amplifier is not suitable.